1. Field of Invention
The invention pertains to flash memory and, in particular, to a flash memory structure that has a vertical channel region with multiple gates and the fabrication method thereof.
2. Related Art
Flash memory is one kind of non-volatile memory. It is used to store data in memory unit. Not only can it maintain the memory of data without being charged, it further has the feature of multiple writing/rewriting. Therefore, it has rapidly developed to become the new generation memory device in recent years.
However, all the current flash memory structures have the problem of no scaling. Particularly when the sizes of electronic products and semiconductor devices become smaller, the fabrication of flash memory faces the bottleneck of being unable to satisfy the requirement of small device sizes and good device properties at the same time.
Since the source region, the drain region, and the channel region in the device are located on the same plane, variations in the device size will directly affect the channel length, which in turn forms a restriction in the device size definition.
The conventional flash memory structure is stacked gate flash memory, whose structure is similar to electrically erasable and programmable ROM (EEPROM). It has a control gate and a floating gate stacked on the device channel. It achieves the programming purpose by injecting hot carriers from the drain into the floating gate. Although the stacked gate flash memory has the advantage of a simpler structure for minimizing the device size, the hot carrier injection efficiency is very low. As the device size shrinks, not only is the channel length shortened, the area of the floating gate and the control gate stacked on the channel also has to decrease. This reduces the capacitance between the floating gate and the control gate, causing increase in the operating voltage.
To increase the hot carrier injection rate, most people add gate units. For example, in one type of source injection flash memory, there are three gate units. In addition to the stacked control gate and the floating gate, an injection gate is further provided above the source to induce the injection of hot carriers from the source to the floating gate. Although this type of flash memory can increase the hot carrier injection efficiency with the installation of the injection gate, the addition injection gate results in a larger device size.
There is also a split-gate flash memory structure, which has the same advantage as the source injection flash memory. By increasing the size of the control gate, the coupling ratio between the control gate and the floating gate and the hot carrier injection efficiency can be simultaneously increased, thereby lowering the operating voltage. Nonetheless, it also has a larger size due to the control gate design.
Therefore, how to keep the desired flash memory characteristics while at the same time minimizing the device size is an important research trend in the field. Moreover, as the device size becomes smaller, the punch-through or breakdown phenomenon may happen due to the short carrier channel. This will damage the device and reduce the device reliability.